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? freescale semiconductor, inc., 2004. all rights reserved. ? preliminary freescale semiconductor hardware specification mcf5275ec/d rev. 1.1, 9/2004 technical data table of contents the mcf5275 family is a highly integrated implementation of the coldfire ? family of reduced instruction set computing (r isc) microprocessors. this document describes pertinent features and functions characteristics of the mcf5275 family. the mcf5275 family includes the mcf5275, mcf5275l, MCF5274 and MCF5274l microprocessors. the differences between these parts are summarized in table 1 . this document is written from the perspective of the mcf5275 and unless otherwis e noted, the information applies also to the mcf5275l, MCF5274 and MCF5274l. the mcf5275 family deli vers a new level of performance and integrati on on the popular version 2 coldfire core with up to 159 (dhrystone 2.1) mips @ 166mhz. these highly integrated microprocessors build upon the widely used peripheral mix on the popular mcf5272 coldfire microprocessor (10/100 mbps ethernet mac and usb de vice) by adding a second 10/100 mbps ethernet ma c (MCF5274 and mcf5275) and hardware encrypti on (mcf5275l and mcf5275). in addition, the mcf5275 family features an enhanced multiply accumulate unit (emac), large on-chip 1 mcf5275 family configurations ..................... 2 2 block diagram ................................................. 3 3 features .......................................................... 5 4 signal descriptions........................................ 17 5 chip configuration......................................... 32 6 design recommendations ............................ 34 7 pinout ............................................................ 42 8 mechanicals .................................................. 45 9 ordering information ..................................... 47 10 preliminary electrical characteristics............ 47 11 device/family documentation list ................ 74 12 document revision history ........................... 74 mcf5275 integrated microprocessor family hardware specification 32-bit embedded controller division
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary mcf5275 family configurations freescale semiconductor 2 memory (64 kbytes sram, 16 kbytes configur able cache), and a 16-bit ddr sdram memory controller. these devices are ideal for cost-sensitive applicati ons requiring significant control processing for file management, connectivity, data buffering, and user interf ace, as well as signal processing in a variety of key markets such as security, imaging, networki ng, gaming, and medical. th is leading package of integration and high performance allows fast time to market through easy code reuse and extensive third party tool support. to locate any published errata or updates for this doc ument, refer to the coldfire products website at http://www.freescale.com . 1 mcf5275 family configurations table 1. mcf5275 family configurations module 5274l 5275l 5274 5275 coldfire version 2 core with emac (enhanced multiply-accumulate unit) xxxx system clock up to 166 mhz performance (dhrystone 2.1 mips) up to 159 instruction/data cache 16 kbytes (configurable) static ram (sram) 64 kbytes interrupt controllers (intc) 2 2 2 2 edge port module (eport) x x x x external interface module (eim) x x x x 4-channel direct-memor y access (dma) x x x x ddr sdram controller x x x x fast ethernet controller (fec) 1 1 2 2 watchdog timer module (wdt) x x x x 4-channel programmable interval timer module (pit) x x x x 32-bit dma timers 4 4 4 4 usb x x x x qspi x x x x uart(s) 3 3 3 3 i 2 cxxxx pwm 4 4 4 4 general purpose i/o module (gpio) x x x x cim = chip configuration module + reset controller module x x x x
block diagram mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 3 2 block diagram the superset device in the mc f5275 family comes in a 256 mold array plastic ball grid array (mapbga) package. figure 1 shows a top-level block diagram of the mcf5275, the superset device. debug bdm x x x x jtag - ieee 1149.1 test access port x x x x hardware encryption ? x ? x package 196 mapbga 196 mapbga 256 mapbga 256 mapbga table 1. mcf5275 family configurations module 5274l 5275l 5274 5275
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary block diagram freescale semiconductor 4 figure 1. mcf5275 block diagram 64 kbytes sram (8kx16)x4 eim v2 coldfire cpu intc0 watchdog pit0 jtag tap cache (1kx32)x4 pit1 pit2 pit3 4 ch dma uart 0 uart 1 i 2 c qspi dtim 0 dtim 1 dtim 2 dtim 3 timer pll clkgen uart 2 16 kbytes edge port sdramc chip ebi selects (to/from padi) (to/from ports cim (gpio) div emac dreq [1:0] intc1 arbiter (to/from sram backdoor) (to/from arbiter backdoor) skha rnga mdha cryptography modules dack [3:0] bdm (to/from intc) mux padi) jtag_en padi ? pin muxing bs [3:2] pwmx usb fec0 dtinx dtoutx rxdx txdx i2c_sda i2c_scl ddr qspi rtsx ctsx d[31:16] a[23:0] r/ w cs [3:0] ta tsiz [1:0] tea fec1 jtag_en trst tclk tms tdi tdo (to/from padi) (to/from padi) fast ethernet controller (fec1) fast ethernet controller (fec0) 4 ch pwm (to/from padi) usb 2.0 full speed (to/from padi)
features mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 5 3features this document contains information on a new product. specifi cations and informati on herein are subject to change without notice. 3.1 feature overview ? coldfire version 2 variable-length risc processor ? static operation ? 32-bit address and data path on-chip ? 166/133 mhz processor core and 83/66.5 mhz bus frequency ? sixteen general-purpose 32-bit data and address registers ? enhanced multiply accumula te unit (emac) for dsp and fast multiply operations ? system debug support ? real time trace for dete rmining dynamic execution path while in emulator mode ? background debug mode (bdm) fo r debug features while halted ? real time debug support, with two user visible hardware breakpoint regi sters (pc and address with optional data) that can be confi gured into a 1- or 2-level trigger ? on chip memories ? 16 kbyte cache, configurable as i-cache or i-cache and d-cache ? 64 kbyte dual-ported sram on cpu internal bus with standby power supply support ? power management ? fully static operation with proce ssor sleep and whole chip stop modes ? very rapid response to interrupts from th e low-power sleep mode (wake-up feature) ? two fast ethernet media access controllers (fec mac) ? 10 base t capability, half or full duplex ? 100 base t capability, half or full duplex throughput ? on chip transmit and receive fifos ? built-in dma controller ? memory-based flexible descriptor rings ? media independent interface (mii) ? usb device module ? supports full-speed 12-mbps and low-speed 1.5-mbps usb devices ? full compliance with the universal serial bus specification, revision 2.0 ? automatic hardware processing of usb standard device requests ? supports external usb transceiver ? protocol control and administration for up to four endpoints (programmable types)
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary features freescale semiconductor 6 ? one fifo ram per endpoint (2-kbyte total) ? dedicated 1-kbyte descriptor ra m, accessible from the slave bus ? remote wake-up ? hardware cryptography accelerator (optional) ? random number generator ? des/3des/aes block cipher engine ? md5/sha-1/hmac accelerator ? three universal asynchronous/synchronous receiver transmitters (uarts) ? serial communication channel ? 16-bit divider for clock generation ? internal channel control logic ? interrupt control logic ? maskable interrupts ? dma support ? programmable clock-rate generator ? data formats can be 5, 6, 7 or 8 bits with even, odd or no parity ? up to 2 stop bits in 1/16 increments ? error-detection capabilities ? modem support includes request-to-send (rts) and clear-to-send (cts) lines ? transmit and receive fifo buffers ?i 2 c module ? interchip bus interface for eeproms, lcd controllers, a/d converters, and keypads ? fully compatible with industry-standard i 2 c bus ? master or slave modes support multiple masters ? automatic interrupt genera tion with programmable level ? queued serial peripheral interface (qspi) ? full-duplex, three-wire synchronous transfer ? up to four chip selects available ? master operation ? programmable master bit rates ? up to 16 preprogrammed transfers ? four 32-bit timers with dma request capability ? pulse width modulation (pwm) unit ? four identical channels ? software watchdog timer
features mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 7 ? 16-bit counter ? low power mode support ? phase locked loop (pll) ? reference crystal 8 to 25 mhz ? low power modes supported ? separate clkout and ddr_clkout signals ? four programmable interrupt timers (pits) ? interrupt controllers (x2) ? support for 58 independent interrupt sources, organized as follows: ? 51 fully-programmable interrupt sources ? 7 fixed-level external interrupt sources ? unique vector number fo r each interrupt source ? ability to mask any individual interrupt sour ce or all interrupt s ources (global mask-all) ? support for hardware and software interrupt acknowledge (iack) cycles ? combinatorial path to provide wake-up from lo w power modes ? dma controller ? four fully programmable channels ? dual-address and single-address transfer s upport with 8-, 16-, and 32-bit data capability ? source/destination address pointers that can increment or remain constant ? 24-bit transfer counter per channel ? auto-alignment transfers supporte d for efficient block movement ? bursting and cycle steal support ? two-bus-clock internal access ? external request pins for each channel ? external memory interface ? external glueless connections to 8-, 16-, a nd 32-bit external memory devices (e.g., sram, flash, rom, etc.) ? glueless interface to sram devices with or without byte strobe inputs ? programmable wait state generator ? 16-bit external bidirectional data bus ? 24-bit address bus ? eight chip selects ? byte/write enables ? ability to boot from external me mories that are 8 or 16 bits wide ? ddr sdram controller
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary features freescale semiconductor 8 ? supports 16-bit wide memory devices ? supports dual data rate (ddr) sdram. ? page mode support ? programmable refresh interval timer. ? sleep mode and self-refresh. ? supports 16-byte (4-beat, 4-byte) crit ical-word-first burst transfer. ? memory sizes from 8 mbyte to 128 mbyte (per chip select) ? 166 mhz data transfer rate (ddr) ? two independent chip selects ?reset ? separate reset in and reset out signals ? six sources of reset (por, external, software, watchdog, loss of clock/lock) ? status flag indication of source of last reset ? chip configurations ? system configuration during reset ? bus monitor, abort monitor ? configurable output pad drive strength ? unique part identification and part revision numbers ? general purpose i/o interface ? up to 69 bits of general purpose i/o ? coherent 32-bit control ? bit manipulation supporte d via set/clear functions ? unused peripheral pins may be used as extra gpio ? jtag support for system level board testing ? unique jtag part identificat ion and part revision numbers 3.2 v2 core overview the coldfire v2 core is comprised of two separate pipelines that are decoupled by an instruction buffer. the two-stage instruction fetch pipeline (ifp) is responsible for instructi on-address generation and instruction fetch. the instruction buffer is a first- in-first-out (fifo) buffe r that holds prefetched instructions awaiting execution in the operand execut ion pipeline (oep). the oep includes two pipeline stages. the first stage decodes in structions and selects operands (dsoc); the second stage (agex) performs instruction execution and calculates operand effective addresses, if needed. the v2 core implements the coldfire instruction set architecture revision a with added support for a separate user stack pointer register and four new instru ctions to assist in bit processing. additionally, the v2 core includes the enhanced multiply-accumu late unit (emac) for im proved signal processing capabilities. the emac implements a 4-stage execu tion pipeline, optimized for 32 x 32 bit operations,
features mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 9 with support for four 48-bit accumu lators. supported operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands as well as a complete set of instructions to process these data types. the emac provides superb support for executi on of dsp operations within the context of a single processor at a minimal hardware cost. 3.3 debug module the coldfire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator deve lopment tools. through a standard debug interface, users can access real-time trace and debug information. this allows the processor and syst em to be debugged at full speed without the need for costly in-circuit emulators. th e debug interface is a supers et of the bdm interface provided on motorola?s 683xx family of parts. the on-chip breakpoint resources incl ude a total of 6 programmable regi sters?a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), and one 32-bit pc register plus a 32-bit pc mask register. these regi sters can be accessed through the dedicated debug serial communi cation channel or from the proces sor?s supervisor mode programming model. the breakpoint registers can be configured to generate triggers by combining the address, data, and pc conditions in a variety of singl e or dual-level definitions. the tr igger event can be programmed to generate a processor halt or in itiate a debug interrupt exception. to support program trace, the version 2 debug m odule provides processor status (pst[3:0]) and debug data (ddata[3:0]) ports. these bus es and the pstclk output provide ex ecution status, captured operand data, and branch target addresses defining processor activity at the cpu?s clock rate. 3.4 jtag the mcf5275 microprocessors suppor t circuit board test strategies based on the test technology committee of ieee and the joint test action group (jtag). the test logic includes a test access port (tap) consisting of a 16-state controller, an instruct ion register, and three test registers (a 1-bit bypass register, a 326-bit boundary-scan regist er, and a 32-bit id register). the boundary scan register links the device?s pins into one shift register . test logic, implemented using stat ic logic design, is independent of the device system logic. the mcf5275 implementation can do the following: ? perform boundary-scan operations to test circuit board electrical continuity ? sample mcf5275 system pins during operation and transparently shift out the result in the boundary scan register ? bypass the mcf5275 for a given circuit board test by effectively reducing the boundary-scan register to a single bit ? disable the output drive to pi ns during circuit-board testing ? drive output pins to stable levels
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary features freescale semiconductor 10 3.5 on-chip memories the 64 kbyte data ram and the 16 kb yte cache ram for the processors are built using a ram compiler. both ram blocks connect directly to the ram controller via a standard single- port synchronous sram interface. 3.5.1 cache the 16-kbyte cache can be configur ed into one of three possible or ganizations: a 16-kbyte instruction cache, a 16-kbyte data cache or a split 8-kbyte inst ruction/8-kbyte data cach e. the configuration is software-programmable by control bits within the privileged cache conf iguration register (cacr). in all configurations, the cache is a di rect-mapped single-cycle memory. 3.5.2 sram the sram module provides a general-purpose 64-kbyt e memory implemented as four 16-kbyte blocks that the coldfire core can access in a single cycle. the location of the memory block can be set to any 64-kbyte boundary within the 4-gbyte address space. the memory is ideal for stori ng critical code or data structures, for use as the system stack, or for st oring fec data buffers. because the sram module is physically connected to the processor's high-speed local bus, it can quickly service co re-initiated accesses or memory-referencing commands from the debug module. the sram module is also accessible by non-core bus masters, for example the dma and/or the fecs. the dual-ported nature of the sram makes it ideal for implementing applic ations with double-buffer schemes, where the processor and a dma device operate in alternate regions of the sram to maximize system performance. as an exampl e, system performance can be incr eased significantly if ethernet packets are moved from the fec into the sram (rather than external memory) prior to any processing. 3.6 power management the mcf5275 family incorporates several low pow er modes of operation which are entered under program control and exited by several external trigger events. an integr ated power-on reset (por) circuit monitors the input supply and forces an mcu reset as the supply voltage rises. 3.7 fast ethernet controller (fec) the mcf5275 family contains up to two 10/100 baset fast ethernet controllers (fecs). refer to table 1 for device configurations. each fec includes these distinctive features: ? ieee 802.3 mac (compliant with ieee 802.3 1998 edition) ? built-in fifo and dma controller ? support for different ethe rnet physical interfaces: ? 100mbps ieee 802.3 mii ? 10mbps ieee 802.3 mii
features mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 11 ? support for full-duplex operation (200mbps thr oughput) with a minimum system clock of 50mhz ? support for half-duplex operation (100mbps throughput) with a mini mum system clock rate of 25mhz ? ieee 802.3 full duplex flow control ? programmable max frame length supports ieee 802.1 vl an tags and priority ? retransmission from transmit fifo follow ing a collision (no system bus utilization) ? automatic internal flushing of the receive fifo for runts (c ollision fragments) and address recognition rejects (no sy stem bus utilization) ? address recognition ? frames with broadcast a ddress may be always accep ted or always rejected ? exact match for single 48-bit individual (unicast) address ? hash (64-bit hash) check of individual (unicast) addresses ? hash (64-bit hash) check of group (multicast) addresses ? promiscuous mode ? rmon and ieee statistics ? interrupts for network act ivity and error conditions 3.8 universal serial bus (usb) the usb controller supports device mode data co mmunications with a us b host (typically a pc). the programmable usb registers allow th e user to enable or disable the module, control characteristics of individual endpoints, and monitor traf fic flow through the module without ever seeing the low-level details of the usb protocol. the usb module provides the foll owing features to the user: ? supports full-speed 12-mbps usb de vices and low-speed 1.5-mbps devices ? full compliance with the universal serial bus specification, revision 2.0 ? automatic hardware processing of usb standard device requests ? usb device controller with pr otocol control and administrati on for up to eight endpoints, 16 interfaces, and 16 configurations. endpoint types are programmable with support for up to eight control, interrupt, bulk, or isochronous endpoints ? independent interrupts for each endpoint ? supports remote wakeup via a register bit ? detects start-of-frame and mi ssed start-of-frame for isoc hronous endpoint synchronization ? notification of start-of-frame, reset, suspend, and resume events
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary features freescale semiconductor 12 3.9 cryptography some of the mcf5275 family devices incorporate smal l, fast, and dedicated ha rdware accelerators for random number generation, message digest and hashing, and the de s, 3des, and aes block cipher functions. this allows for the implementation of common internet securi ty protocol cryptography operations with performance well in exces s of software-only algorithms. refer to table 1 for device configurations. 3.10 uarts the mcf5275 family of microprocessors each contain three (3) uarts that function independently. any of the three uarts can be clocked by the system bus clock, eliminating the need for an external crystal. each uart module contains the fo llowing major functional features: ? serial communication channel ? 16-bit divider for clock generation ? internal channel control logic ? interrupt control logic ? maskable interrupts ? dma support ? programmable clock-rate generator ? data formats can be 5, 6, 7 or 8 bits with even, odd or no parity ? up to 2 stop bits in 1/16 increments ? error-detection capabilities ? modem support includes request-to-send (rts) and clear-to-send (cts) lines ? transmit and receive fifo buffers ? uart modes of operation: ? full-duplex ? auto-echo loopback ? local loopback ? remote loopback 3.11 i 2 c bus the i 2 c is a two-wire, bidirectional seri al bus that provides a simple, ef ficient method of data exchange, minimizing the interconnection between devices. this bus is suitable for applications re quiring occasional communications over a short distance between many de vices. the flexible i 2 c allows additional devices to be connected to the bus for expansion and system development. the i 2 c includes these distinctive features: ? compatibility with i 2 c bus standard
features mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 13 ? multiple-master operation ? software programmable for one of 64 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven, byt e-by-byte data transfer ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection ? dma support 3.12 qspi the queued serial peripheral interf ace module provides a serial periphe ral interface with queued transfer capability. it allows users to enqueue up to 16 tran sfers at once, eliminating cpu intervention between transfers. transfer rams in the qspi are indi rectly accessible using address and data registers. the qspi contains th e following features: ? programmable queue to support up to 16 transfers without user intervention ? supports transfer sizes of 8 to 16 bits in 1-bit increments ? four peripheral chip-select lines ? baud rates from 162.1 kbps to 20.75 mbps at 83 mhz ? programmable delays before and after transfers ? programmable clock phase and polarity ? supports wraparound mode for continuous transfers 3.13 dma timers (dtim0-dtim3) there are four independent, gene ral purpose 32-bit platform timers (dtim0, dtim1, dtim2, dtim3) on the mcf5275 family of micropro cessors. the output of an 8-bit prescaler clocks each timer. each of the platform timer modules has these distinctive features: ? programmable sources for the cloc k input, including external clock ? input capture capability with progr ammable trigger edge on input pin ? output compare with programmable mode for the output pin ? free run and restart modes ? maskable interrupts on input cap ture or reference compare ? dma support
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary features freescale semiconductor 14 each of the four timer modu les has four operating modes: ? capture mode ? output mode ? reference compare mode 3.14 pulse width modulation (pwm) module the pulse width modulation (pwm) module gene rates a synchronous series of pulses having programmable duty cycle. w ith a suitable low-pass filter, the pwm can be used as a digital-to-analog converter. the pwm module has six channels wi th independent control of left and center aligned outputs on each channel. the mcf5275 family uses f our of these channels namely 0, 1, 2 and 3. the emergency shutdown functionality (channel 5 only) is not used for the mcf5275 family. each of the pwm channels has a programmable period and duty cycle as well as a dedicated counter. a flexible clock select scheme allows a total of four different clock sources to be used with the counters. each of the modulators can create indepe ndent continuous waveforms with so ftware-selectable duty rates from 0% to 100%. the pwm outputs can be programmed as left aligned outputs or center aligned outputs summary of the main features include: ? independent pwm channels with programmable period and duty cycle ? dedicated counter for each pwm channel ? programmable pwm enable/disable for each channel ? software selection of pwm duty pulse polarity for each channel ? period and duty cycle are double buffered. change takes effect when the end of the effective period is reached (pwm counter reaches zer o) or when the channel is disabled. ? programmable center or left al igned outputs on individual channels ? 16-bit pwm resolution available by concatenating 8-bit channels ? four clock sources (a, b, sa and sb) provide for a wide range of frequencies. ? programmable clock select logic 3.15 software watchdog timer (wdt) the watchdog timer is a 16-bit timer for helping software recover from runaway code. the watchdog counter is a free-running dow n-counter that generates a reset on underf low. to prevent a reset, software must periodically re start the countdown. 3.16 phase locked loop (pll) the clock module contains a crysta l oscillator (osc), frequency modulated phase-locked loop (pll), reduced frequency divider (rfd), stat us/control registers, and control l ogic. to improve noise immunity,
features mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 15 the pll and osc have their own power supply input s, vddpll and vsspll. all other circuits are powered by the normal supply pins, vdd and vss. 3.17 interrupt controllers (intc0/intc1) there are two interrupt controll ers which support 58 interrupt sour ces on the mcf5275. each interrupt controller is organized as 7 levels with 9 interrupt sources per level. each interrupt source has a unique interrupt vector, and 51 of the 58 sources of a give n controller provide a progr ammable level [1-7] and priority within the level. 3.18 direct memory access controller (dmac) the direct memory access controller (dma) module provides an efficien t way to move blocks of data with minimal processor interacti on. the dma module provides four cha nnels that allow byte, word, or longword operand transfers. these tr ansfers can be single or dual addr ess to off-chip devices or dual address to on-chip devices. the dma contains the following features: ? four fully independent, programmable dma controller channels/bus modules ? auto-alignment feature for s ource or destination accesses ? single- and dual- address transfers ? up to four external request pins (dreq [3:0]) ? channel arbitration on transfer boundaries ? data transfers in 8-, 16-, 32- or 128-bit blocks via a 16-byte buffer ? supports continuous-mode a nd cycle-steal transfers ? independent transfer widths for source and destination ? independent source and dest ination address registers ? provide two cloc k data transfers 3.19 external interface module (eim) the external interface module on mc f5275 devices handles the transfer of information between the internal core and memory, peripherals, or other pr ocessing elements in the external address space. programmable chip select outputs provide signals to enable exte rnal memory and peripheral circuits, providing all handshaking a nd timing signals for automatic wait-s tate insertion and data bus sizing. base memory address and bl ock size are programmable, with some re strictions. for example, the starting address must be on a boundary that is a multiple of th e block size. each chip se lect is general purpose; however, any one of the chip selects can be programmed to provide read and write enable signals suitable for use with most popular static rams and periphera ls. data bus width (8-bit , 16-bit, or 32-bit) is programmable on all chip selects, and further decodi ng is available for protection from user mode access or read-only access.
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary features freescale semiconductor 16 the key features of the eim are summarized below: ? eight independent, user-program mable chip-select signals (cs[7: 0]) that interface with various memory types and peripherals ? address masking for 64 kbyte to 4 gigabyte memory block sizes ? programmable wait states and port sizes ? external master access to chip selects 3.20 double data rate (ddr) synchronous dram (sdram) controller the sdramc provides a 16-bit glue less external interface to doubl e-data-rate (ddr) sdram memory devices. it is responsible for pr oviding address, data and control signals for up to two independent chip-selects. the sdramc includes the following features: ? supports a glueless interface to ddr sdrams ? 16-bit fixed memory port width ? 32-bit data bus interface to coldfire core ? 16 bytes (8 beat x 16-bit) cr itical word first burst transfer ? up to 14 row address lines, up to 12 column a ddress lines, maximum of two chip selects. the maximum row bits plus column bits is 24. ? supported sdram devices include: 8, 16, 32, 64, and 128mbyte per chip select ? minimum memory configuration of 8 mbyte?12 bit row address (ra), 8 bit column address (ca), 2 bit bank address (ba) and one chip select ? supports page mode to maximize the data rate ? supports sleep mode and self-refresh mode ? error detect and parity check are not supported 3.21 resets the reset controller is provided to de termine the cause of reset, assert the appropriate reset signals to the system, and then to keep a hist ory of what caused the reset. the mcf5275 family has si x (6) sources of reset: ? external ? power on reset (por) ? watchdog timer ? pll loss of lock ? pll loss of clock ? software
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 17 external reset on the rstout pin is software-assertabl e independent of chip reset state. there are also software-readable status flags indi cating the cause of the last reset. 3.22 general purpose i/o most peripheral i/o pins on mcf 5275 devices are muxed with gpio, a dding flexibility and usability to all signals on the chip. 4 signal descriptions table 2 lists the signals for the mcf5275 in functional group order. note in this table and throug hout this document a singl e signal within a group is designated without square brackets (i.e., a24), wh ile designations for multiple signals within a group use br ackets (i.e., a[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. note the primary functionality of a pin is not necessarily its de fault functionality. pins that are muxed with gpio will default to their gpio functionality. table 2. signal information and muxing name gpio port alternate1 alternate2 dir. 1 bonded on MCF5274/75 256 mapbga bonded on MCF5274l/5l 196 mapbga reset reset ? ?? i1 1 rstout ? ?? o1 1 clock extal ? ?? i1 1 xtal ? ?? o1 1 clkout ? ?? o1 1 mode selection clkmod[1:0] ? ?? i 2 2 rcon ? ?? i1 1 external memory interface and ports a[23:21] paddr[7:5] cs [6:4] ? o 3 3
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary signal descriptions freescale semiconductor 18 a[20:0] ? ? ? o 21 21 d[31:16] ? ?? o 16 16 bs [3:2] pbs [3:2] cas [3:2] ? o 2 2 oe pbusctl[7] ? ? o 1 1 ta pbusctl[6] ? ? i1 1 tea pbusctl[5] dreq1 ?i1 0 r/w pbusctl[4] ? ? o 1 1 tsiz1 pbusctl[3] dack1 ? o 1 1 tsiz0 pbusctl[2] dack0 ? o 1 1 ts pbusctl[1] dack2 ? o 1 1 tip pbusctl[0] dreq0 ? o 1 0 chip selects cs [7:1] pcs[7:1] ? ? o 7 7 cs0 ? ? ? o 1 1 ddr sdram controller ddr_clkout ? ?? o1 1 ddr_clkout ? ?? o1 1 sd_cs [1:0] psdram[7:6] cs [3:2] ? o 2 2 sd_sras psdram[5] ? ? o 1 1 sd_scas psdram[4] ? ? o 1 1 sd_we psdram[3] ? ? o 1 1 sd_a10 ???o 1 1 sd_dqs [1:0] psdram[1:0] ??i/o 2 2 sd_cke psdram[2] ? ? o 1 1 sd_vref ? ? ? i 2 2 external interrupts port irq [7:5] pirq[7:5] ?? i3 3 irq [4] pirq[4] dreq2 ? i1 1 irq [3:2] pirq[3:2] dreq [3:2] ? i2 2 irq1 pirq[1] ?? i1 1 table 2. signal information and muxing (continued) name gpio port alternate1 alternate2 dir. 1 bonded on MCF5274/75 256 mapbga bonded on MCF5274l/5l 196 mapbga
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 19 fec0 fec0_mdio pfeci2c[5] i2c_sda u2rxd i/o 1 1 fec0_mdc pfeci2c[4] i2c_scl u2txd o 1 1 fec0_txclk pfec0h[7] ?? i 1 1 fec0_txen pfec0h[6] ?? i 1 1 fec0_txd[0] pfec0h[5] ?? o 1 1 fec0_col pfec0h[4] ?? i 1 1 fec0_rxclk pfec0h[3] ?? i 1 1 fec0_rxdv pfec0h[2] ?? i 1 1 fec0_rxd[0] pfec0h[1] ?? i 1 1 fec0_crs pfec0h[0] ?? i 1 1 fec0_txd[3:1] pfec0l[7:5] ?? o 3 3 fec0_txer pfec0l[4] ?? o 1 1 fec0_rxd[3:1] pfec0l[3:1] ?? i 3 3 fec0_rxer pfec0l[0] ?? o 1 1 fec1 fec1_mdio pfeci2c[3] ?? i/o 1 0 fec1_mdc pfeci2c[2] ?? o 1 0 fec1_txclk pfec1h[7] ?? i 1 0 fec1_txen pfec1h[6] ?? i 1 0 fec1_txd[0] pfec1h[5] ?? o 1 0 fec1_col pfec1h[4] ?? i 1 0 fec1_rxclk pfec1h[3] ?? i 1 0 fec1_rxdv pfec1h[2] ?? i 1 0 fec1_rxd[0] pfec1h[1] ?? i 1 0 fec1_crs pfec1h[0] ?? i 1 0 fec1_txd[3:1] pfec1l[7:5] ?? o 3 0 fec1_txer pfec1l[4] ?? o 1 0 fec1_rxd[3:1] pfec1l[3:1] ?? i 3 0 fec1_rxer pfec1l[0] ?? o 1 0 table 2. signal information and muxing (continued) name gpio port alternate1 alternate2 dir. 1 bonded on MCF5274/75 256 mapbga bonded on MCF5274l/5l 196 mapbga
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary signal descriptions freescale semiconductor 20 i 2 c i2c_sda pfeci2c[1] u2rxd ? i/o 1 1 i2c_scl pfeci2c[0] u2txd ? i/o 1 1 dma dack [3:0] and dreq [3:0] do not have a dedicated bond pads. please refer to the following pins for muxing: pcs3/pwm3 for dack3 , pcs2/pwm2 for dack2 , tsiz1 for dack1 , tsiz0 for dack0 , irq3 for dreq3 , irq2 and ta for dreq2 , tea for dreq1 , and tip for dreq0 . ? ? qspi qspi_cs[3:2] pqspi[6:5] pwm[3:2] dack [3:2] o 2 2 qspi_cs1 pqspi[4] sd_cke ? o 1 1 qspi_cs0 pqspi[3] ? ? o 1 1 qspi_clk pqspi[2] i2c_scl ? o 1 1 qspi_din pqspi[1] i2c_sda ? i 1 1 qspi_dout pqspi[0] ? ? o 1 1 uarts u0cts puartl[0] ? ? i 1 1 u0rts puartl[1] ? ? o 1 1 u0rxd puartl[3] ? ? i 1 1 u0txd puartl[2] ? ? o 1 1 u1cts puartl[4] ? ? i 1 1 u1rts puartl[5] ? ? o 1 1 u1rxd puartl[7] ? ? i 1 1 u1txd puartl[6] ? ? o 1 1 u2cts puarth[1] pwm1 ? i 1 0 u2rts puarth[0] pwm0 ? o 1 0 u2rxd puarth[3] ? ? i 1 0 u2txd puarth[2] ? ? o 1 0 usb usb_speed pusbh[0] ? ? i/o 1 1 table 2. signal information and muxing (continued) name gpio port alternate1 alternate2 dir. 1 bonded on MCF5274/75 256 mapbga bonded on MCF5274l/5l 196 mapbga
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 21 usb_clk pusbl[7] ? ? i 1 1 usb_rn pusbl[6] ? ? i 1 1 usb_rp pusbl[5] ? ? i 1 1 usb_rxd pusbl[4] ? ? i 1 1 usb_susp pusbl[3] ? ? o 1 1 usb_tn pusbl[2] ? ? o 1 1 usb_tp pusbl[1] ? ? o 1 1 usb_txen pusbl[0] ? ? o 1 1 timers (and pwms) dt3in ptimer[7] dt3out u2rts i 1 1 dt3out ptimer[6] pwm3 u2cts o 1 1 dt2in ptimer[5] dt2out ? i 1 1 dt2out ptimer[4] pwm2 ? o 1 1 dt1in ptimer[3] dt1out ? i 1 1 dt1out ptimer[2] pwm1 ? o 1 1 dt0in ptimer[1] dt0out ? i 1 1 dt0out ptimer[0] pwm0 ? o 1 1 bdm/jtag 2 dsclk ? trst ? i 1 1 pstclk ? tclk ? o 1 1 bkpt ? tms ? i 1 1 dsi ? tdi ? i 1 1 dso ? tdo ? o 1 1 jtag_en ? ? ? i 1 1 ddata[3:0] ? ? ? o 4 4 pst[3:0] ? ? ? o 4 4 test test ? ? ? i 1 1 pll_test ? ? ? i 1 1 power supplies table 2. signal information and muxing (continued) name gpio port alternate1 alternate2 dir. 1 bonded on MCF5274/75 256 mapbga bonded on MCF5274l/5l 196 mapbga
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary signal descriptions freescale semiconductor 22 4.1 reset signals table 3 describes signals that are used to either reset the chip or as a reset indication. 4.2 pll and clock signals table 4 describes signals that are used to s upport the on-chip clock generation circuitry. vddpll ? ? ? i 1 1 vsspll ? ? ? i 1 1 vdd ? ? ? i vss ? ? ? i ovdd ? ? ? i ovss ? ? ? i sd_vdd ? ? ? i notes: 1 refers to pin?s primary function. all pins which are configurable for gpio have a pullup enabled in gpio mode with the excepti on of pbusctl[7], pbusctl[4:0], paddr, pbs, psdram. 2 if jtag_en is asserted, these pins default to alternate 1 (jtag) functionality. the gpio module is not responsible for assigning these pins. table 3. reset signals signal name abbreviation function i/o reset in reset primary reset input to the device. asserting reset immediately resets the cpu and peripherals. i reset out rstout driven low for 128 cpu clocks when the soft reset bi t of the system configuration register (scr[softrst]) is set. it is driven low for 32k cpu clocks when the software watchdog timer times out or when a low input level is applied to reset . o table 2. signal information and muxing (continued) name gpio port alternate1 alternate2 dir. 1 bonded on MCF5274/75 256 mapbga bonded on MCF5274l/5l 196 mapbga
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 23 4.3 mode selection table 5 describes signals used in mode selection. 4.4 external memory interface signals these signals are used for doing tr ansactions on the external bus. table 6 describes signals that are used for doing transactions on the external bus. table 4. pll and clock signals signal name abbreviation function i/o external clock in extal always driven by an external clock input except when used as a connection to the external crystal when the internal oscillator circuit is used. the clock source is configured during reset by clkmod[1:0]. i crystal xtal used as a connection to the external crystal when the internal oscillator circuit is used to drive the crystal. o clock out clkout this output signal reflects the internal system clock. o table 5. mode selection signals signal name abbreviation function i/o clock mode selection clkmod[1:0] conf igure the clock mode after reset. i reset configuration rcon indicates whether the external d[31:16] pin states affect chip configuration at reset. i table 6. external memory interface signals signal name abbreviation function i/o address bus a[23:0] the 24 dedicated address si gnals define the address of external byte, word, and longword accesses. these three-state outputs are the 24 lsbs of the internal 32-bit address bus and multiplexed with the sdram controller row and column addresses. o data bus d[31:16] these three-state bidirect ional signals provide the general purpose data path between the processor and all other devices. i/o
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary signal descriptions freescale semiconductor 24 4.5 ddr sdram controller signals table 7 describes signals that are used for ddr sdram accesses. byte strobes bs [3:2] define the flow of data on the data bus. during sram and peripheral accesses, these output signals indicate that data is to be latched or driven onto a byte of the data when driven low. the bs [3:2] signals are asserted only to the memory bytes used during a read or write access. bs 3 controls access to the most significant byte lane of data, and bs 2 controls access to the least significant byte lane of data. the bs [3:2] signals are asserted during accesses to on-chip peripherals but not to on-chip sram, or cache. during sdram accesses, these signals act as the cas [3:2] signals, which indicate a byte transfers between sdram and the chip when driven high. for sram or flash devices, the bs [3:2] outputs should be connected to individual byte strobe signals. for sdram devices, the bs [3:2] should be connected to individual sdram dqm signals. note that mo st sdrams associate dqm1 with the msb, in which case bs 3 should be connected to the sdram's dqm1 input. o output enable oe indicates when an external device can drive data during external read cycles. o transfer acknowledge ta indicates that the external data transfer is complete. during a read cycle, when the processor recognizes ta , it latches the data and then terminates the bus cycle. during a write cycle, when the processor recognizes ta , the bus cycle is terminated. i transfer error acknowledge tea indicates an error condi tion exists for the bus transfer. the bus cycle is terminated and the cpu begins execution of the access error exception. i read/write r/w indicates the direction of the data transfer on the bus for sram (r/w ) and sdram (sd_we ) accesses. a logic 1 indicates a read from a slave device and a logic 0 indicates a write to a slave device o transfer size tsiz [1:0] when the device is in normal mode, dynamic bus sizing lets the programmer change data bus width between 8, 16, and 32 bits for each chip select. the initial widt h for the bootstrap program chip select, cs0, is determin ed by the state of tsiz [1:0]. the program should select bus widths for the ot her chip selects before accessing the associated memory space. these pins our output pins. o transfer start ts bus control output signal indicating the start of a transfer. o transfer in progress tip bus control output signal indicating bus transfer in progress. o chip selects cs [7:0] these output signals select external devices for external bus transactions. the cs [3:2] can also be configured to function as sdram chip selects sd_cs [1:0]. o table 6. external memory interface signals (continued) signal name abbreviation function i/o
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 25 4.6 external interrupt signals table 8 describes the external interrupt signals. 4.7 fast ethernet controller signals the following signals are used by the ethe rnet modules for data and clock signals. table 7. sdram controller signals signal name abbreviation function i/o sdram clock out ddr_clkout this output signa l reflects the internal system clock. o sdram inverted clock out ddr_clkout this output signal refl ects the inverted internal system clock. o sdram synchronous row address strobe sd_sras sdram synchronous row address strobe. o sdram synchronous column address strobe sd_scas sdram synchronous column address strobe. o sdram write enable sd_we sdram write enable. o sdram a10 sd_a10 sdram address bit 10 or command. o sdram chip selects sd_cs [1:0] sdram chip select signals. o sdram clock enable sd_cke sdram clock enable. o sdram data strobes sd_dqs [3:2] sdram byte-lane read/write data strobe signals. o table 8. external interrupt signals signal name abbreviation function i/o external interrupts irq [7:1] external interrupt sources. irq [3:2] can also be configured as dma request signals dreq [3:2]. irq4 can also be configured as dma request signals dreq2 . i table 9. ethernet module (fec) signals signal name abbreviation function i/o management data fec n _mdio transfers control information between the external phy and the media-access controller. data is synchronous to fec n _mdc. applies to mii mode operation. this signal is an input after reset. when the fec is operated in 10mbps 7-wire interface mode, this signal should be connected to vss. i/o management data clock fec n _mdc in ethernet mode, fec n _mdc is an output clock which provides a timing reference to the phy for data transfers on the fec n _mdio signal. applies to mii mode operation. o transmit clock fec n _txclk input clock which provides a timing reference for fec n _txen, fec n _txd[3:0] and fec n _txer i
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary signal descriptions freescale semiconductor 26 4.8 queued serial peripheral interface (qspi) table 10 describes qspi signals. transmit enable fec n _txen indicates when valid nibbles are present on the mii. this signal is asserted with the first nibble of a preamble and is negated before the first fec n _txclk following the final nibble of the frame. o transmit data 0 fec n _txd0 fec n _txd0 is the serial output ethern et data and is only valid during the assertion of fec n _txen. this signal is used for 10-mbps ethernet data. it is also used fo r mii mode data in conjunction with fec n _txd[3:1]. o collision fec n _col asserted upon detection of a collision and remains asserted while the collision persists. this signal is not defined for full-duplex mode. i receive clock fec n _rxclk provides a timing reference for fec n _rxdv, fec n _rxd[3:0], and fec n _rxer. i receive data valid fec n _rxdv asserting the receive data valid (fec n _rxdv) input indicates that the phy has valid nibbles present on the mii. fec n _rxdv should remain asserted from the first recovered nibb le of the frame through to the last nibble. assertion of fec n _rxdv must start no later than the sfd and exclude any eof. i receive data 0 fec n _rxd0 fec n _rxd0 is the ethernet input data transferred from the phy to the media-access controller when fec n _rxdv is asserted. this signal is used for 10-mbps ethernet da ta. this signal is also used for mii mode ethernet data in conjunction with fec n _rxd[3:1]. i carrier receive sense fec n _crs when asserted, indicates that transmit or receive medium is not idle. applies to mii mode operation. i transmit data 1?3 fec n _txd[3:1] in ethernet mode, these pins co ntain the serial output ethernet data and are valid only during assertion of fec n _txen in mii mode. o transmit error fec n _txer in ethernet mode, when fec n _txer is asserted for one or more clock cycles while fec n _txen is also asserted, the phy sends one or more illegal symbols. fec n _txer has no effect at 10 mbps or when fec n _txen is negated. applies to mii mode operation. o receive data 1?3 fec n _rxd[3:1] in ethernet mode, these pi ns contain the ethernet input data transferred from the phy to the media access controller when fec n _rxdv is asserted in mii mode operation. i receive error fec n _rxer in ethernet mode, fec n _rxer?when asserted with fec n _rxdv?indicates that the phy has detected an error in the current frame. when fec n _rxdv is not asserted fec n _rxer has no effect. applies to mii mode operation. o table 9. ethernet module (fec) signals (continued) signal name abbreviation function i/o
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 27 4.9 i 2 c i/o signals table 11 describes the i 2 c serial interface module signals. 4.10 uart module signals the uart modules use the signals in this section fo r data. the baud rate cloc k inputs are not supported. table 10. queued serial peripheral interface (qspi) signals signal name abbreviation function i/o qspi syncrhonous serial output qspi_dout provides the serial data from t he qspi and can be programmed to be driven on the rising or falling edge of qspi_clk. each byte is sent msb first. o qspi synchronous serial data input qspi_din provides the serial data to the qspi and can be programmed to be sampled on the rising or falling edge of qspi_clk. each byte is written to ram lsb first. i qspi serial clock qspi_clk provides the serial cl ock from the qspi. the polarity and phase of qspi_clk are programmable. the output frequency is programmed according to the following formula, in which n can be any value between 1 and 255: spi_clk = f sys /2 n o synchronous peripheral chip selects qspi_cs[1:0] provide qspi peripheral chip selects that can be programmed to be active high or low. qspi_cs1 can also be configured as sdram clock enable signal sd_cke. o table 11. i 2 c i/o signals signal name abbreviation function i/o serial clock i2c_scl open-drain clock signal for the for the i 2 c interface. either it is driven by the i 2 c module when the bus is in the master mode or it becomes the clock input when the i 2 c is in the slave mode. i/o serial data i2c_sda open-drain signal that serves as the data input/output for the i 2 c interface. i/o table 12. uart module signals signal name abbreviation function i/o transmit serial data output u n txd transmitter serial data outputs for the uart modules. the output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. data is shifted out, lsb first, on this pin at the falling edge of the serial clock source. o receive serial data input u n rxd receiver serial data inputs for the uart modules. data received on this pin is sampled on the rising edge of the serial clock source lsb first. when the uart clock is stopped for power-down mode, any transition on this pin restarts it. i
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary signal descriptions freescale semiconductor 28 4.11 usb signals table 13 describes the usb serial interface module signals. clear-to-send u n cts indicate to the uart modules that they can begin data transmission. i request-to-send u n rts automatic request-to-send outputs from the uart modules. u n rts can also be configured to be asserted and negated as a function of the rxfifo level. o table 13. usb module signals signal name abbreviation function i/o usb clock usb_clk this 48mhz (or 6mhz) clock is used by the usb module for both clock recovery and generation of a 12mhz (or 1.5mhz) internal bit clock. i usb speed usb_speed applications which make use of low speed usb signalling must be able to switch the usb transceiver between low speed and full speed operations. software has control of th is function by driving the state of the usb_spd bit in the usb_ctrl register onto the usb_speed pin. i/o usb received d- usb_rn this signal is one half of the differential usb signal, and is extracted from the usb cable via a single ended input buffer on the analog front end. this signal is used by the module for detecting the single ended 0 (se0) usb bus state. i usb received d+ usb_rp this signal is one half of the differential usb signal, and is extracted from the usb cable via a single ended input buffer on the analog front end. this signal is used by the module for detecting the single ended 0 (se0) usb bus state. i usb receive data usb_rxd input data from the differential input receiver. usb_rxd is the single-ended data extracted from the usb_rp and usb_rn signals via a differential input buffer. i usb suspended usb_susp after a long period of inactivity (3.0ms minimum), the usb will enter suspend mode, indicated on the interface by an active state on usb_susp. during this mode, the de vice is supposed to enter a low power state while waiting for a wake-up from the usb host. when the device enters suspend mode, it asserts the suspend signal which forces the analog front end into a low power state. when the device leaves suspend mode, usb_susp is deasserted, enabling the analog front end for normal usb operations. o usb transmitted d- usb_tn this signal is one half of the differential nrz i formatted output from the usb module. it is fed to the tr ansmitted d- input of the analog front end. o table 12. uart module signals (continued) signal name abbreviation function i/o
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 29 4.12 dma timer signals table 14 describes the signals of the four dma timer modules. 4.13 pulse width modulator signals table 15 describes the pwm signals. note that the primary functions of these pins are dma timer outputs (dt n out). usb transmitted d+ usb_tp this signal is one half of the differential nrz i formatted output from the module. it is fed to the transmi tted d+ input of the analog front end. o usb transmit enable usb_txen this signal is an active low output enable for the differential drivers on the analog front end. when this signal is active, the differential drivers will drive the usb. when this signal is inactive, the differential drivers will tristate their outputs. o table 14. dma timer signals signal name abbreviation function i/o dma timer 0 input dt0in can be programmed to cause events to occur in first platform timer. it can either clock the event counter or provide a trigger to the timer value capture logic. i dma timer 0 output dt0out the output from first platform timer. o dma timer 1 input dt1in can be programmed to caus e events to occur in the second platform timer. this can either clock the even t counter or provide a trigger to the timer value capture logic. i dma timer 1 output dt1out the output from the second platform timer. o dma timer 2 input dt2in can be programmed to caus e events to occur in the third platform timer. it can either clock the event counter or provide a trigger to the timer value capture logic. i dma timer 2 output dt2out the output from the third platform timer. i dma timer 3 input dt3in can be programmed as an in put that causes events to occur in the fourth platform timer. this can either clock the event counter or provide a trigger to the timer value capture logic. i dma timer 3 output dt3out the output from the fourth platform timer. o table 13. usb module signals (continued) signal name abbreviation function i/o
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary signal descriptions freescale semiconductor 30 4.14 debug support signals these signals are used as the interface to the on-chi p jtag controller and also to interface to the bdm logic. table 15. pwm signals signal name abbreviation function i/o pwm output channel 0 pwm0 pulse width modulated output for pwm channel 0. o pwm output channel 1 pwm1 pulse width modulated output for pwm channel 1. o pwm output channel 2 pwm2 pulse width modulated output for pwm channel 2. o pwm output channel 3 pwm3 pulse width modulated output for pwm channel 3. o table 16. debug support signals signal name abbreviation function i/o test reset trst this active-low signal is used to initialize the jtag logic asynchronously. i test clock tclk used to synch ronize the jtag logic. i test mode select tms used to sequence the jtag state machine. tms is sampled on the rising edge of tclk. i test data input tdi serial input for test instru ctions and data. tdi is sampled on the rising edge of tclk. i test data output tdo serial output for test inst ructions and data. tdo is three-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tclk. o development serial clock dsclk clocks the serial communication port to the bdm module during packet transfers. i breakpoint bkpt used to request a manual breakpoint. i development serial input dsi this internally-synchronized signal provides data input for the serial communication port to the bdm module. i development serial output dso this internally-registered signal pr ovides serial output communication for bdm module responses. o debug data ddata[3:0] display captured processor data and breakpoint status. the clkout signal can be used by the development system to know when to sample ddata[3:0]. o processor status outputs pst[3:0] indicate core status, as shown in ta b l e 1 7 . debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. the clkout signal can be used by the development system to know when to sample pst[3:0]. o
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 31 4.15 test signals table 18 describes test signals. 4.16 power and ground pins the pins described in table 19 provide system power and ground to th e chip. multiple pins are provided for adequate current capability. all power supply pins must have adequate bypass capacitance for high-frequency noise suppression. table 17. processor status pst[3:0] processor status 0000 continue execution 0001 begin execution of one instruction 0010 reserved 0011 entry into user mode 0100 begin execution of pulse and wddata instructions 0101 begin execution of taken branch 0110 reserved 0111 begin execution of rte instruction 1000 begin one-byte transfer on ddata 1001 begin two-byte transfer on ddata 1010 begin three-byte transfer on ddata 1011 begin four-byte transfer on ddata 1100 exception processing 1101 reserved 1110 processor is stopped 1111 processor is halted table 18. test signals signal name abbreviation function i/o test test reserved for factory testing only and in normal modes of operation should be connected to vss to prevent unintentional activation of test functions. i pll test pll_test reserved for factory testing only and should be treated as a no-connect (nc). i
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary chip configuration freescale semiconductor 32 5 chip configuration 5.1 device operating options ? chip operating mode: ? master mode ? boot device/size: ? external device boot ? 32-bit ? 16-bit (default) ?8-bit ? output pad strength: ? partial drive strength (default) ? full drive strength ? clock mode: ? normal pll with external crystal ? normal pll with external clock ? 1:1 pll mode ? external oscillator mode (no pll) ? chip select configuration: ? paddr[7:5] configured as chip select(s) and/or address line(s) ? paddr[7:5] configured as a23-a21 (default) ? paddr configured as cs6 , paddr[6:5] as a22-a21 ? paddr[7:6] configured as cs [6:5], paddr5 as a21 ? paddr[7:5] configured as cs [6:4] table 19. power and ground pins signal name abbreviation function i/o pll analog supply vddpll, vsspll dedicated power supply signals to isolate the sensitive pll analog circuitry from the normal levels of noise present on the digital power supply. i positive supply vddo these pins supply positive power to the i/o pads . i positive supply vdd these pins supply positive power to the core logic. i ground vss this pin is the negative supply (ground) to the chip.
chip configuration mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 33 5.2 chip configuration pins 5.3 chip configuration circuit figure 2 shows a block diagram of the recommended circui t used to drive the reset configuration values for the mcf5275. table 20. configuration pin descriptions pin chip configuration function pin state/meaning comments rcon chip configuration enable 1 disabled 0 enabled active low: if asserted, then all configuration pins must be driven appropriately for desired operation d26, d17, d16 select chip operating mode 111 master 110 reserved 101 reserved 100 reserved 0xx reserved d19, d18 select external boot device data port size 00,11 external (32-bit) 10 external (8-bit) 01 external (16-bit) value read defaults to 32-bit d21 select output pad drive strength 1full 0 partial clkmod1, clkmod0 select clock mode 00 external clock mode (no pll) 01 1:1 pll mode 10 normal pll with external clock reference 11 normal pll with crystal clock reference vddpll must be supplied if a pll mode is selected d25, d24 select chip select / address line 00 paddr[7:5] configured as a23-a21 (default) 10 paddr7 configured as cs6 , paddr[6:5] as a22-a21 01 paddr[7:6] configured as cs [6:5], paddr5 as a21 11 paddr[7:5] configured as cs [6:4] jtag_en selects bdm or jtag mode 0bdm mode 1 jtag mode
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary design recommendations freescale semiconductor 34 figure 2. mcf5275 recommended reset configuration circuit 6 design recommendations 6.1 layout ? use a 4-layer printed circuit board with the v dd and gnd pins connected directly to the power and ground planes for the mcf5275. ? see application note an1259 system design and layout techniques for noise reduction in mcu-based systems. ? match the pc layout trace wi dth and routing to match trace length to operating frequency and board impedance. add terminat ion (series or therein) to the traces to dampen reflections. increase the pcb impedance (if possible) keepi ng the trace lengths balanced and short. then do cross-talk analysis to separate traces with significant parallelis m or are otherwise "noisy". use 6 mils trace and separation. clocks get extr a separation and more precise balancing. 6.2 power supply ? 33uf, 0.1uf and 0.01uf across each power supply inputs driven high or low as needed 74hc244 d17 d18 d19 d21 d24 d25 vdd/vss d16 mcf5275 jtag_en clkmod1 clkmod0 rcon rstout oe d26
design recommendations mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 35 6.3 decoupling ? place the decoupling capacitors as close to the pins as possible, but they can be outside the footprint of the package. ? 0.1uf and 0.01uf at each supply input 6.4 buffering ? use bus buffers on all data/address lines for al l off-board accesses and for all on-board accesses when excessive loading is expected. see electricals. 6.5 pull-up recommendations ? use external pull-up resistors on unused inputs. see pin table. 6.6 clocking recommendations ? use a multi-layer board wi th a separate ground plane. ? place the crystal and all other associated components as close to the extal and xtal (oscillator pins) as possible. ? do not run a high frequency trace around crystal circuit. ? ensure that the ground for the bypass capaci tors is connected to a solid ground trace. ? tie the ground trace to the ground pin nearest extal and xtal. this prevents large loop currents in the vicinity of the crystal. ? tie the ground pin to the most solid ground in the system. ? do not connect the trace that connects the oscill ator and the ground plane to any other circuit element. this tends to ma ke the oscillator unstable. ? tie xtal to ground when an external oscillator is clocking the device. 6.7 interface recommendations 6.7.1 ddr sdram controller 6.7.1.1 sdram controller signals in synchronous mode table 21 shows the behavior of sdra m signals in synchronous mode.
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary design recommendations freescale semiconductor 36 6.7.1.2 address multiplexing table 22 shows the generic address mult iplexing scheme for sdram confi gurations. all possible address connection configurations can be derived from this table. table 21. synchronous dram signal connections signal description sd_sras synchronous row address strobe. indicates a valid sdram row address is present and can be latched by the sdram. sd_sras should be connected to the corresponding sdram sd_sras . do not confuse sd_sras with the dram controller?s sdram_cs[1:0] , which should not be interfaced to the sdram sd_sras signals. sd_scas synchronous column address strobe. indicates a valid column address is present and can be latched by the sdram. sd_scas should be connected to the corresponding signal labeled sd_scas on the sdram. sd_we dram read/write. asserted for write operations and negated for read operations. sd_cs [1:0] row address strobe. select each memory block of sdrams connected to the mcf5275. one sdram_cs signal selects one sdram block and connects to the corresponding cs signals. sd_cke synchronous dram clock enable. connected directly to the cke (clock enable) signal of sdrams. enables and disables the clock internal to sdram. when cke is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. sd_cke functionality is controlled by dcr[coc]. for designs using external multiplexing, setting coc allows sd_cke to provide command-bit functionality. bs [3:2] column address strobe. for synchronous operation, bs [3:2] function as byte enables to the sdrams. they connect to the dqm signals (or mask qualifiers) of the sdrams. ddr_clkout bus clock output. connects to the clk input of sdrams. table 22. generic address multiplexing scheme address pin row address column address notes related to port sizes 17 17 0 8-bit port only 16 16 1 8- and 16-bit ports only 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 99 8 17 17 16 32-bit port only 18 18 17 16-bit port only or 32-bit port with only 8 column address lines 19 19 18 16-bit port only when at least 9 column address lines are used 20 20 19 21 21 20
design recommendations mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 37 the following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for inte rfacing the mcf5275 to sdram. to use the tables, find the one that corresponds to the number of column address lines on the sdram and to the port size as seen by the mcf5275, which is not necessarily the sdram port size. for exampl e, if two 8m x 8-bit sdrams together form a 8m x 16-bit memory, the port size is 16 bits. most sdrams likely have fewer address lines than are shown in the tables, so follow onl y the connections shown until all sdram address lines are connected. 22 22 21 23 23 22 24 24 23 25 25 24 table 23. mcf5275 to sdram interface (8-bit port, 9-column address lines) mcf5275 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a18 a19 a2 0a21a22a23a24a25a26a27a28a29a30a31 row 1716151413121110 9 1819202122232425262728293031 column 012345678 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 table 24. mcf5275 to sdram interface (8-bit port,10-column address lines) mcf5275 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 19202122232425262728293031 column 01234567818 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 table 25. mcf5275 to sdram interface (8-bit port,11-column address lines) mcf5275 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 192122232425262728293031 column 0123456781820 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 table 22. generic address multiplexing scheme (continued) address pin row address column address notes related to port sizes
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary design recommendations freescale semiconductor 38 table 26. mcf5275 to sdram interface (8-bit port,12-column address lines) mcf5275 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 1921232425262728293031 column 012345678182022 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 table 27. mcf5275 to sdram interface (8-bit port,13-column address lines) mcf5275 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a23 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 19212325262728293031 column 01234567818202224 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 table 28. mcf5275 to sdram interface (16-bit port, 8-column address lines) mcf5275 pins a16 a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 column 12345678 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 table 29. mcf5275 to sdram interface (16-bit port, 9-column address lines) mcf5275 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16 15 14 13 12 11 10 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 column 1234567817 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 table 30. mcf5275 to sdram interface (16-bit port, 10-column address lines) mcf5275 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16151413121110 9 18202122232425262728293031 column 123456781719 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20
design recommendations mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 39 table 31. mcf5275 to sdram interface (16-bit port, 11-column address lines) mcf5275 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16 15 14 13 12 11 10 9 18 20 22 23 24 25 26 27 28 29 30 31 column 1 2 3 4 5 6 7 8 17 19 21 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 table 32. mcf5275 to sdram interface (16-bit port, 12-column address lines) mcf5275 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a24 a25 a26 a27 a28 a29 a30 a31 row 16 15 14 13 12 11 10 9 18 20 22 24 25 26 27 28 29 30 31 column 1234567817192123 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 table 33. mcf5275 to sdram interface (16-bit port, 13-column-address lines) mcf5275 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a24 a26 a27 a28 a29 a30 a31 row 16151413121110 9 18202224262728293031 column 1 2 3 4 5 6 7 8 17 19 21 23 25 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 table 34. mcf5275 to sdram interface (32-bit port, 8-column address lines) mcf5275 pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a2 1a22a23a24a25a26a27a28a29a30a31 row 151413121110 9 171819202122232425262728293031 column 234567816 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 table 35. mcf5275 to sdram interface (32-bit port, 9-column address lines) mcf5275 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 1719202122232425262728293031 column 23456781618 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary design recommendations freescale semiconductor 40 6.7.1.2.1 sdram interfacing example the tables in the previous section can be used to configure the interface in the following example. to interface one 2m x 32-bit x 4 bank sdram component (8 columns) to the mcf5275, the connections would be as shown in table 39 . 6.7.2 ethernet phy transceiver connection the fec supports both an mii interfac e for 10/100 mbps ethernet and a se ven-wire serial interface for 10 mbps ethernet. the interface mode is select ed by r_cntrl[mii_mode]. in mii mode, the 802.3 standard defines and the fec module s upports 18 signals. these are shown in table 40 . table 36. mcf5275 to sdram interface (32-bit port, 10-column address lines) mcf5275 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 17192122232425262728293031 column 2345678161820 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 table 37. mcf5275 to sdram interface (32-bit port, 11-column address lines) mcf5275 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 15 14 13 12 11 10 9 17 19 21 23 24 25 26 27 28 29 30 31 column 2 3 4 5 6 7 8 16 18 20 22 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 table 38. mcf5275 to sdram interface (32-bit port, 12-column address lines) mcf5275 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a23 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 1719212325262728293031 column 2 3 4 5 6 7 8 1618202224 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 table 39. sdram hardware connections sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 = cmd ba0 ba1 mcf5275 pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22
design recommendations mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 41 the serial mode interface operates in what is generally referred to as amd mode. the mcf5275 configuration for seven-wire seri al mode connections to the exte rnal transceiver are shown in table 41 . refer to the m5275evbevaluation board user?s manual for an example of how to connect an external phy. schematics for this board are accessi ble at the mcf5275 site by navigating from: http://e-www.motorola. com/ following the 32-bit embedded processors, 68k/coldfire, mcf5xxx, mcf5275 and m5275evb links. table 40. mii mode signal description mcf5275 pin transmit clock fec n _txclk transmit enable fec n _txen transmit data fec n _txd[3:0] transmit error fec n _txer collision fec n _col carrier sense fec n _crs receive clock fec n _rxclk receive enable fec n _rxdv receive data fec n _rxd[3:0] receive error fec n _rxer management channel clock fec n _mdc management channel serial data fec n _mdio table 41. seven-wire mode configuration signal description mcf5275 pin transmit clock fec n _txclk transmit enable fec n _txen transmit data fec n _txd[0] collision fec n _col receive clock fec n _rxclk receive enable fec n _rxdv receive data fec n _rxd[0] unused, configure as pb14 fec n _rxer unused input, tie to ground fec n _crs unused, configure as pb[13:11] fec n _rxd[3:1] unused output, ignore fec n _txer unused, configure as pb[10:8] fec n _txd[3:1] unused, configure as pb15 fec n _mdc input after reset, connect to ground fec n _mdio
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary pinout freescale semiconductor 42 6.7.3 bdm use the bdm interface as shown in the m5275evb ev aluation board user?s manual. the schematics for this board are accessible at the mcf5275 site by navigating from: http://e-www.mot orola.com/ following the 32-bit embedded processors, 68k/coldf ire, mcf5xxx, mcf5275 and m5275evb links. 7pinout 7.1 256 mapbga pinout figure 3 is a consolidated MCF5274/75 pinout for the 256 mapbga package. table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages.
pinout mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 43 figure 3. MCF5274 and mcf5275 pinout (256 mapbga) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a vss fec1_ rxd1 fec1_ rxdv fec1_ crs fec1_ col fec0_ col fec0_ mdio u0rxd u1rxd vss a23 a20 a17 a14 sd_ vref vss a b fec1_ rxd3 fec1_ rxd2 fec1_ rxd0 fec1_ rxclk fec0_ rxdv fec0_ rxclk fec0_ mdc u0txd u1txd i2c_ sda a22 a19 a16 a13 a11 a9 b c fec1_ txclk fec1_ rxer fec0_ txclk fec0_ rxer fec0_ rxd2 fec0_ rxd0 fec0_ crs u0cts u1cts i2c_ scl a21 a18 a15 a12 a10 a8 c d fec1_ txer fec1_ txen fec0_ txer fec0_ txen fec0_ rxd3 fec0_ rxd1 u0rts vdd u1rts cs7 cs6 cs5 cs4 a7 a6 tsiz1 d e fec1_ txd3 fec1_ txd2 fec0_ txd3 nc vss ovdd ovdd ovdd sd_vdd sd_vdd sd_vdd vss cs3 a5 a4 a3 e f fec1_ txd0 fec1_ txd1 fec0_ txd2 fec0_ txd1 ovdd vss ovdd ovdd sd_vdd sd_vdd vss sd_vdd cs2 a2 a1 a0 f g fec1_ mdio fec1_ mdc dt0out fec0_ txd0 ovdd ovdd vss vss vss vss sd_vdd sd_vdd irq7 usb_ speed usb_ clk tsiz0 g h dt1in dt1out dt0in nc ovdd ovdd vss vss vss vss sd_vdd sd_vdd vdd irq4 irq5 irq6 h j vss dt2in dt2out dt3in sd_vdd sd_vdd vss vss vss vss ovdd ovdd irq2 irq3 usb_rp usb_rn j k oe sd_we dt3out vdd sd_vdd sd_vdd vss vss vss vss ovdd ovdd irq1 usb_tn usb_tp vsspll k l sd_ scas sd_ sras sd_cke ts sd_vdd vss sd_vdd sd_vdd ovdd ovdd vss ovdd ta usb_ txen usb_ rxd extal l m d31 sd_cs1 bs3 sd_dqs3 vss sd_vdd sd_vdd sd_vdd ovdd ovdd ovdd nc usb_ susp pll_ test vddpll xtal m n d30 d29 d28 d20 d16 sd_a10 cs1 vdd test ddata2 ddata0 qspi_ cs2 clk mod1 rstout reset vss n p d27 d26 d23 d19 sd_dqs2 tip r/w rcon u2cts ddata3 ddata1 qspi_ cs0 clk mod0 trst / dsclk tdo/ dso tclk/ pstclk p r d25 d24 d22 d18 bs2 cs0 vss u2rts u2txd pst2 pst0 qspi_ dout qspi_ cs3 jtag_ en tms/ bkpt tdi/dsi r t vss sd_ vref d21 d17 sd_cs0 ddr_clk out ddr_clk out tea u2rxd pst3 pst1 clkout qspi_ din qspi_ cs1 qspi_ clk vss t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary pinout freescale semiconductor 44 7.2 196 mapbga pinout figure 4 is a consolidated MCF5274l/75l pinout for the 196 mapbga package. table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages. figure 4. MCF5274l and mcf5275l pinout (196 mapbga) 1234567891011121314 a nc fec0_ crs fec0_ mdio u0rxd u0txd u1rxd i2c_scl a23 cs6 cs5 a15 a12 sd_ vref nc a b fec0_ rxd2 fec0_ rxd1 fec0_ rxclk fec0_ col u0rts u1rts i2c_sda a22 a20 a16 a13 cs3 a9 tsiz1 b c fec0_ txclk fec0_ txer fec0_ txen fec0_ rxdv fec0_ mdc u0cts u1cts a21 a18 a17 a14 a10 a8 cs2 c d fec0_ txd3 fec0_ txd0 fec0_ txd1 fec0_ rxd3 fec0_ rxd0 vdd u1txd cs7 a19 cs4 a11 a7 a5 a2 d e dt0in dt0out fec0_ txd2 fec0_ rxer ovdd ovdd ovdd sd_vdd2 sd_vdd2 sd_vdd2 a6 a4 a1 tsiz0 e f dt1in dt1out dt2in dt2out ovdd ovdd vss vss sd_vdd2 sd_vdd2 a3 usb_clk a0 irq7 f g dt3out dt3in sd_cas sd_we vdd vss vss vss vss sd_vdd2 usb_ speed vdd irq6 irq5 g h sd_sras ts sd_cs1 oe sd_vdd1 vss vss vss vss ovdd irq4 irq2 usb_rn irq3 h j sd_cke sd_dqs3 d31 d22 sd_vdd1 sd_vdd1 vss vss ovdd ovdd usb_rp usb_tp irq1 usb_tn j k bs3 d29 d28 d23 sd_vdd1 sd_vdd1 sd_vdd1 ovdd ovdd ovdd tdo/dso reset usb_ txen ta k l d30 d26 d25 d24 bs2 r/w vdd pst2 ddata0 qspi_ dout qspi_clk rstout vsspll usb_rxd l m d27 d21 d18 d17 sd_cs0 rcon ddata3 pst1 qspi_ cs0 qspi_din clkmod1 tdi/dsi vddpll extal m n d20 d19 d16 sd_a10 cs0 test ddata2 pst0 qspi_ cs2 qspi_ cs1 clkmod0 tms/bkpt usb_ susp xtal n p nc sd_ vref sd_dqs2 cs1 ddr_clk out ddr_clk out pst3 ddata1 clkout qspi_ cs3 jtag_en tclk/pst clk trst /dsc lk nc p 1234567891011121314
mechanicals mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 45 8 mechanicals 8.1 package dimensions - 256 mapbga figure 6 shows mcf5275 256 mapbga package dimensions. figure 5. 256 mapbga package dimensions 8.2 package dimensions - 196 mapbga figure 6 shows mcf5275 196 mapbga package dimensions. x y d e laser mark for pin a1 identification in this area 0.20 metalized mark for pin a1 identification in this area m m 3 a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 10 11 12 13 14 15 16 e 15x e 15x b 256x m 0.25 y z m 0.10 x z s detail k view m-m rotated 90 clockwise s a z z a2 a1 4 0.15 z 0.30 256x 5 k notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.25 1.60 a1 0.27 0.47 a2 1.16 ref b 0.40 0.60 d 17.00 bsc e 17.00 bsc e 1.00 bsc s 0.50 bsc
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary mechanicals freescale semiconductor 46 figure 6. 196 mapbga package dimensions x 0.20 laser mark for pin 1 identification in this area e 13x d e m s a1 a2 a 0.15 z 0.30 z z rotated 90 clockwise detail k 5 view m-m e 13x s m x 0.30 y z 0.10 z 3 b 196x metalized mark for pin 1 identification in this area 14 13 12 11 5 4 3 2 b c d e f g h j k l 4 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.32 1.75 a1 0.27 0.47 a2 1.18 ref b 0.35 0.65 d 15.00 bsc e 15.00 bsc e 1.00 bsc s 0.50 bsc y k m n p a 1 6 10 9
ordering information mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 47 9 ordering information 10 preliminary electrical characteristics this appendix contains electrical specification tables and refere nce timing diagrams for the mcf5275 microcontroller unit. this section contains deta iled information on power considerations, dc/ac electrical characteristi cs, and ac timing spec ifications of mcf5275. the electrical specifications are preliminary and are from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specificat ions will be met. finalized speci fications will be published after complete characterization and device qualifications have been completed. note the parameters specified in this appe ndix supersede any values found in the module specifications. 10.1 maximum ratings table 42. orderable part numbers motorola part number description speed temperature MCF5274lvm133 MCF5274l risc microprocessor, 196 mapbga 133mhz 0 to +70 c MCF5274lvm166 MCF5274l risc microprocessor, 196 mapbga 166mhz 0 to +70 c MCF5274vm133 MCF5274 risc microprocessor, 256 mapbga 133mhz 0 to +70 c MCF5274vm166 MCF5274 risc microprocessor, 256 mapbga 166mhz 0 to +70 c mcf5275lcvm133 mcf5275l risc microprocessor, 196 mapbga 133mhz -40 to +85 c mcf5275lcvm166 mcf5275l risc microprocessor, 196 mapbga 166mhz -40 to +85 c mcf5275cvm133 mcf5275 risc microprocessor, 256 mapbga 133mhz -40 to +85 c mcf5275cvm166 mcf5275 risc microprocessor, 256 mapbga 166mhz -40 to +85 c table 43. absolute maximum ratings 1, 2 rating symbol value unit core supply voltage v dd ? 0.5 to +2.0 v i/o pad supply voltage (3.3v) o v dd ? 0.3 to +4.0 v memory interface sstl 2.5v pad supply voltage sd v dd ? 0.3 to + 2.8 v memory interface sstl 3.3v pad supply voltage sd v dd ? 0.3 to +4.0 v clock synthesizer supply voltage v ddpll ? 0.3 to +4.0 v digital input voltage 3 v in ? 0.3 to + 4.0 v extal pin voltage v extal 0 to 3.3 v xtal pin voltage v xtal 0 to 3.3 v
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 48 10.2 thermal characteristics table 44 lists thermal resistance values table 44. thermal characteristics instantaneous maximum current single pin limit (applies to all pins) 4, 5 i d 25 ma operating temperature range (packaged) t a (t l - t h ) ? 40 to 85 c storage temperature range t stg ? 65 to 150 c notes: 1 functional operating conditions are given in dc el ectrical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. 2 this device contains circuitry protecting against damag e due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circui t. reliability of operation is enhanced if unused inputs are tied to an appropriate lo gic voltage level (e.g., either v ss or o v dd ). 3 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 all functional non-supply pins are internally clamped to v ss and o v dd . 5 power supply must maintain regulation within operating o v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > o v dd ) is greater than i dd , the injection current may flow out of o v dd and could result in external power supply going out of regulation. insure external o v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not cons uming power (ex; no clock).power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. characteristic symbol value unit junction to ambient, natural convection 256 mbga four layer board (2s2p) jma 26 1,2 notes: 1 jma and jt parameters are simulated in conformance with eia/jesd standard 51-2 fo r natural convection. motorola recommends the use of jma and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specif ication. system designers sh ould be aware that device junction temperatures can be significantly influenced by boa rd layout and surrounding devices. conformance to the device junction temperature specificat ion can be verified by physical measur ement in the customer?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-6 with the board horizontal. c / w junction to ambient (@200 ft/min) 256 mbga four layer board (2s2p) jma 23 c / w junction to board 256 mbga jb 15 3 3 thermal resistance between the die and the printed ci rcuit board in conformance with jedec jesd51-8. board temperature is measured on the top surface of the board near the package. c / w junction to case 256 mbga jc 10 4 c / w junction to top of package natural convection jt 2 5 c / w maximum operating junction temperature 256 mbga t j 105 o c table 43. absolute maximum ratings 1, 2
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 49 10.3 esd protection 4 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 5 thermal characterization parameter indi cating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written in conformance with psi-jt. the average chip-junction temperature (t j ) in c can be obtained from: (1) where: t a = ambient temperature, c jma = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < p int and can be ignored. an approximate relationship between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + jma p d 2 (3) where k is a constant pertaining to the particular part. k can be determi ned from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . table 45. esd protection characteristics 1, 2 notes: 1 all esd testing is in conformity with cdf -aec-q100 stress test qualification for automotive grade in tegrated circuits. characteristics symbol value units esd target for human body model hbm 2000 v esd target for machine model mm 200 v hbm circuit description r series 1500 ohms c 100 pf mm circuit description r series 0ohms c 200 pf number of pulses per pin (hbm) positive pulses negative pulses ? ? 1 1 ? number of pulses per pin (mm) positive pulses negative pulses ? ? 3 3 ? interval of pulses ? 1 sec t j t a p d jma ( ) + = p d kt j 273 c + () =
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 50 10.4 dc electrical specifications 2 a device is defined as a failure if after ex posure to esd pulses the device no longer meets the device specification requirements. comple te dc parametric and functional testing is performed per applicable device specificatio n at room temperature followed by hot temperature, unless specified other wise in the device specification. table 46. dc electrical specifications 1 notes: 1 refer to table 47 for additional pll specifications. characteristic symbol min max unit core supply voltage v dd 1.35 1.65 v i/o pad supply voltage o v dd 3.0 3.6 v sstl i/o pad supply voltage sd v dd 2.3 2.7 v input high voltage v ih 0.7 x o v dd 3.6 v input low voltage v il v ss ? 0.3 0.35 x o v dd v input high voltage sstl 2.5v i/o pads v ih 2.0 2.8 v input low voltage sstl 2.5v i/o pads v il ? 0.5 0.8 v input high voltage sstl 3.3v i/o pads v ih 2.0 3.6 v input low voltage sstl 3.3v i/o pads v il ? 0.5 0.8 v input hysteresis v hys 0.06 x v dd ?mv input leakage current v in = v dd or v ss , input-only pins i in ?1.0 1.0 a high impedance (off-state) leakage current v in = v dd or v ss , all input/output and output pins i oz ?1.0 1.0 a output high voltage (all inpu t/output and all output pins) i oh = ?2.0 ma v oh o v dd - 0.5 __ v output low voltage (all input/ output and all output pins) i ol = 2.0ma v ol __ 0.5 v weak internal pull up device current, tested at v il max. 2 2 refer to the MCF5274 signals chapter for pins having weak internal pull-up devices. i apu -10 - 130 a input capacitance 3 all input-only pins all input/output (three-state) pins c in ? ? 7 7 pf load capacitance 4 low drive strength high drive strength c l 25 50 pf core operating supply current 5 master mode wait doze stop i dd ? ? ? ? 175 15 10 100 ma ma ma a i/o pad operating supply current master mode low power modes o i dd ? ? 250 250 ma a dc injection current 3, 6, 7, 8 v negclamp =v ss ? 0.3 v, v posclamp = v dd + 0.3 single pin limit total mcu limit, includes sum of all stressed pins i ic -1.0 -10 1.0 10 ma
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 51 10.5 oscillator and phase loc k loop (pllmrfm) electrical specifications 3 this parameter is characterized before qualification rather than 100% tested. 4 pf load ratings are based on dc loading and are provided as an indication of driver strength. high speed interfaces require transmission line analysis to determine proper drive strength and termination. 5 current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. 6 all functional non-supply pins are internally clamped to v ss and their respective v dd . 7 input must be current limited to the va lue specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 8 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. insure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consumi ng power. examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. also, at power-up, system clock is not pres ent during the power-up sequence until the p ll has attained lock. table 47. pll electrical specifications 1 characteristic symbol min max unit pll reference frequency range crystal reference external reference 1:1 mode (note: f sys/2 = 2 f ref_1:1 ) f ref_crystal f ref_ext f ref_1:1 8 8 24 25 25 83 mhz core frequency clkout frequency 2 external reference on-chip pll frequency f core f sys/2 0 f ref / 32 166 83 83 mhz mhz mhz loss of reference frequency 3, 5 f lor 100 1000 khz self clocked mode frequency 4, 5 f scm tbd tbd mhz crystal start-up time 5, 6 t cst ?10ms extal input high voltage crystal mode all other modes (dual controlle r (1:1), bypass, external) v ihext v ihext tbd tbd tbd tbd v extal input low voltage crystal mode all other modes (dual controlle r (1:1), bypass, external) v ilext v ilext tbd tbd tbd tbd v xtal output high voltage i oh = 1.0 ma v oh tbd ? v xtal output low voltage i ol = 1.0 ma v ol ? tbd v xtal load capacitance 7 530pf pll lock time 8 t lpll ? 750 s power-up to lock time 6, 9 with crystal reference without crystal reference 10 t lplk ? ? 11 750 ms s 1:1 mode clock skew (between clkout and extal) 11 t skew -1 1 ns duty cycle of reference 5 t dc 40 60 % f sys/2
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 52 10.6 external interface timing characteristics table 48 lists processor bus input timings. note all processor bus timings are synchr onous; that is, input setup/hold and output delay with respect to the ri sing edge of a reference clock. the reference clock is the clkout output. all other timing relationships ca n be derived fro m these values. frequency un-lock range f ul - 3.8 4.1 % f sys/2 frequency lock range f lck - 1.7 2.0 % f sys/2 clkout period jitter, 5, 6, 9,12, 13 measured at f sys/2 max peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over 2 ms interval) c jitter ? ? 5 .01 % f sys/2 frequency modulation range limit 14 , 15 (f sys/2 max must not be exceeded) c mod 0.8 2.2 % f sys/2 ico frequency. f ico = f ref * 2 * (mfd+2) 16 f ico 48 83 mhz notes: 1 all values given are initial design targets and subject to change. 2 all internal registers retain data at 0 hz. 3 ?loss of reference frequency? is the reference frequency det ected internally, which transitions the pll into self clocked mode. 4 self clocked mode frequency is the frequency that the pl l operates at when the reference frequency falls below f lor with default mfd/rfd settings. 5 this parameter is guaranteed by characterization before qualification rather than 100% tested. 6 proper pc board layout procedures must be followed to achieve specifications. 7 load capacitance determined from cryst al manufacturer specifications and will include circuit board parasitics. 8 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 9 assuming a reference is available at power up, lock time is measured from the time v dd and v ddpll are valid to rstout negating. if the crystal oscillator is being used as the reference for the pll, then the crystal start up time must be added to the pll lock time to determine the total start-up time. 10 t lpll = (64 * 4 * 5 + 5 x ) x t ref , where t ref = 1/f ref_crystal = 1/f ref_ext = 1/f ref_1:1 , and = 1.57x10 -6 x 2(mfd + 2) 11 pll is operating in 1:1 pll mode. 12 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f sys/2 . measurements are made with the device powered by filt ered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the jitter percentage for a given interval. 13 based on slow system clock of 33mhz maximum frequency. 14 modulation percentage applies over an interval of 10 s, or equivalently the modulation rate is 100khz. 15 modulation rate selected must not result in f sys/2 value greater than the f sys/2 maximum specified value. modulation range determined by hardware design. 16 f sys/2 = f ico / (2 * 2 rfd ) table 47. pll electrical specifications 1 characteristic symbol min max unit
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 53 timings listed in table 48 are shown in figure 7 . table 48. processor bus input timing specifications name characteristic 1 notes: 1 timing specifications have been indicated taking into account the full drive strength for the pads. symbol min max unit b0 clkout tcyc 12 ? ns control inputs b1a control input valid to clkout high 2 2 tea and ta pins are being referred to as control inputs. tcvch 9 ? ns b1b bkpt valid to clkout high 3 3 refer to figure a-19. tbkvch 9 ? ns b2a clkout high to control inputs invalid 2 tchcii 0 ? ns b2b clkout high to asynchronous control input bkpt invalid 3 tbknch 0 ? ns data inputs b4 data input (d[31:16]) vali d to clkout high tdivch 4 ? ns b5 clkout high to data input (d[31:16]) invalid tchdii 0 ? ns
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 54 figure 7. general input timing requirements 10.7 processor bus output timing specifications table 49 lists processor bus output timings. table 49. external bus output timing specifications name characteristic symbol min max unit control outputs b6a clkout high to chip selects (cs [7:0]) valid 1 tchcv ? 0.5t cyc + 5 ns b6b clkout high to byte enables (bs [3:2]) valid 2 tchbv ? 0.5t cyc + 5 ns b6c clkout high to output enable (oe ) valid 3 tchov ? 0.5t cyc + 5 ns b7 clkout high to control output (bs [3:2], oe ) invalid tchcoi 0.5t cyc + 1.5 ? ns b7a clkout high to chip selects invalid tchci 0.5t cyc + 1.5 ? ns address and attribute outputs b8 clkout high to address (a[23:0]) and control (ts , tsiz[1:0], tip , r/w) valid tchav ? 9 ns invalid invalid clkout (83mhz) t setup t hold input setup and hold t rise v h = v ih v l = v il valid t fall v h = v ih v l = v il input rise time input fall time * the timings are also valid for inputs sampled on the negative clock edge. inputs clkout b4 b5
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 55 read/write bus timings listed in table 49 are shown in figure 8 , figure 9 , and figure 10 . b9 clkout high to address (a[23:0]) and control (ts , tsiz[1:0], tip , r/w) invalid tchai 1.5 ? ns data outputs b11 clkout high to data output (d[31:16]) valid tchdov ? 9 ns b12 clkout high to data output (d[31:16]) invalid tchdoi 1.5 ? ns b13 clkout high to data output (d[31:16]) high impedance tchdoz ? 9 ns notes: 1 cs transitions after the falling edge of clkout. 2 bs transitions after the falling edge of clkout. 3 oe transitions after the falling edge of clkout. table 49. external bus output timing specifications (continued) name characteristic symbol min max unit
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 56 figure 8. read/write (internally terminated) sram bus timing figure 9 shows a bus cycle terminated by ta showing timings listed in table 49 . clkout csn a[23:0] r/w bs [3:2] d[31:16] ta (h) (h) s0 s2 s3 s1 s4 s5 s0 s1 s2 s3 s4 s5 tea (h) b6a b8 b7a b6c b7 b6b b7 b4 b5 b11 b12 b9 b9 b8 b6b b13 oe b0 b7 b9 ts tip b8 b8 b9 b8 b9 tsiz[1:0] b7a b6a b8
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 57 figure 9. sram read bus cycle terminated by ta figure 10 shows an sram bus cycle terminated by tea showing timings listed in table 49 . clkout csn a[23:0] oe r/w bs [3:2] ta (h) s0 s2 s3 s1 s4 s5 s0 s1 tea (h) b6a b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:16] b4 b5 b8 b9 ts b9 tip b8 tsiz[ 1:0]
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 58 figure 10. sram read bus cycle terminated by tea 10.8 ddr sdram ac timing characteristics the ddr sdram controller uses sstl2 and i/o drivers. either class i or class ii drive strength is available and is user progr ammable. ddr clock timing sp ecifications are given in table 50 and figure 11 . clkout csn a[23:0] oe r/w bs [3:2] tea (h) s0 s2 s3 s1 s4 s5 s0 s1 ta (h) b6a b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:16] b8 b9 ts b9 tip b8 tsiz[ 1:0]
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 59 figure 11. ddr clock timing diagram when using the ddr sdram cont roller the timing numbers in table 51 must be followed to properly latch or drive data onto the memory bus. all timi ng numbers are relative to the two dqs byte lanes. table 50. ddr clock timing specifications 1 notes: 1 sd v dd is nominally 2.5v. symbol characteristic min max unit v mp clock output mid-point voltage 1.05 1.45 v v out clock output voltage level -0.3 sd v dd + 0.3 v v id clock output differential voltage (peak to peak swing) 0.7 sd v dd + 0.6 v v ix clock crossing point voltage 1.05 1.45 v table 51. ddr timing num characteristic 1 notes: 1 all timing specifications are based on taking in to account, a 25pf load on the sdram output pins. symbol min max unit frequency of operation 2 2 ddr_clkout operates at half the frequency of the pllmrfm output and the coldfire core. tbd 83 mhz dd1 clock period (ddr_clkout) t ck 12 tbd ns dd2 pulse width high 3 3 t ckh + t ckl must be less than or equal to t ck . t ckh 0.45 0.55 t ck dd3 pulse width low 3 t ckl 0.45 0.55 t ck dd4 ddr_clkout high to ddr address, sd_cke, sd_cs[1:0], sd_scas, sd_sras, sd_we valid t cmv - 0.5 x t ck + 1 ns dd5 ddr_clkout high to ddr address, sd_cke, sd_cs , sd_scas , sd_sras , sd_we invalid t cmh 2-ns dd6 write command to first sd_dqs latching transition t dqss -1.25t ck dd7 sd_dqs high to data and dm valid (write) - setup 4,5 4 d[31:24] is relative to sd_dqs3 and d[23:16] is relative to sd_dqs2 . t qs 1.5 - ns dd8 sd_dqs high to data and dm invalid (write) - hold 4 t qh 1-ns dd9 sd_dqs high to data valid (read) - setup 6 t is -1ns dd10 sd_dqs high to data invalid (read) - hold 7 t ih 0.25 x t ck + 1 - ns dd11 sd_dqs falling edge to clkout high - setup t dss 0.5 - ns dd12 sd_dqs falling edge to clkout high - hold t dsh 0.5 - ns dd13 dqs input read preamble width (t rpre )t rpre 0.9 1.1 t ck dd14 dqs input read postamble width (t rpst )t rpst 0.4 0.6 t ck dd15 dqs output write preamble width (t wpre )t wpre 0.25 ? t ck dd16 dqs output write postamble width (t wpst )t wpst 0.4 0.6 t ck sdclk sdclk v ix v mp v ix v id
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 60 figure 13 shows a ddr sdram write cycle. figure 12. ddr_clkout and ddr_clkout crossover timing figure 13. ddr write timing 5 the first data beat will be valid before the first rising edge of sd_dqs and after the sd_dqs write preamble. the remaining data beats will be valid for each subsequent sd_dqs edge 6 data input skew is derived from each sd_dqs clock edge. it begins with a sd_dqs transition and ends when the last data line becomes valid. this input skew must include ddr memory ou tput skew and system level board skew (due to routing or other factors). 7 data input hold is derived from each sd_dqs clock edge. it begins with a sd_dqs transition and ends when the first data line becomes invalid. ddr_clkout ddr_clkout v ix v mp v ix v id ddr_clkout sd_cs n ,sd_we , dm[3:2] d[31:16] a[13:0] sd_sras ,sd_scas cmd row dd1 dd5 dd4 col wd1 wd2 wd3 wd4 dd7 sd_dqs [3:2] dd8 dd8 dd7 ddr_clkout dd3 dd2 dd6
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 61 figure 14. ddr read timing 10.9 general purpose i/o timing gpio can be configured for certain pins of th e qspi, ddr control, timers, uarts, fec0, fec1, interrupts and usb interfaces. when in gpio mode the timing specifica tion for these pins is given in table 52 and figure 15 . table 52. gpio timing num characteristic symbol min max unit g1 clkout high to gpio output valid t chpov -10ns g2 clkout high to gpio output invalid t chpoi 1.5 - ns g3 gpio input valid to clkout high t pvch 9-ns g4 clkout high to gpio input invalid t chpi 1.5 - ns clkout sd_csn ,sd_we , sd_dqs [3:2] d[31:16] a[13:0] sd_sras ,sd_scas cmd row dd1 dd5 dd4 wd1 wd2 wd3 wd4 sd_dqs [3:2] dd9 clkout dd3 dd2 d[31:16] wd1 wd2 wd3 wd4 dd10 cl=2 cl=2.5 col dqs read preamble dqs read postamble dqs read preamble dqs read postamble cl = 2.5 cl = 2
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 62 figure 15. gpio timing 10.10 reset and configur ation override timing table 53. reset and configuration override timing (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) 1 notes: 1 all ac timing is shown with respect to 50% o v dd levels unless otherwise noted. num characteristic symbol min max unit r1 reset input valid to clkout high t rvch 9-ns r2 clkout high to reset input invalid t chri 1.5 - ns r3 reset input valid time 2 2 during low power stop, the synchronizers for the reset input are bypassed and reset is asserted asynchronously to the system. thus, reset must be held a minimum of 100 ns. t rivt 5-t cyc r4 clkout high to rstout valid t chrov -10ns r5 rstout valid to config. overrides valid t rovcv 0-ns r6 configuration override setup time to rstout invalid t cos 20 - t cyc r7 configuration override hold time after rstout invalid t coh 0-ns r8 rstout invalid to configuration override high impedance t roicz - 1 x t cyc ns g1 clkout gpio outputs g2 g3 g4 gpio inputs
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 63 figure 16. reset and configuration override timing 10.11 fast ethernet ac timing specifications mii signals use ttl signal levels compatible with devices operating at either 5.0 v or 3.3 v. 10.11.1mii receive signal timing (fec n _rxd[3:0], fec n _rxdv, fec n _rxer, and fec n _rxclk) the receiver functions co rrectly up to a fec n _rxclk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the pr ocessor clock frequency must exceed twice the fec n _rxclk frequency. table 54 lists mii receive channel timings. figure 17 shows mii receive sign al timings listed in table 54 . table 54. mii receive signal timing num characteristic min max unit m1 fec n _rxd[3:0], fec n _rxdv, fec n _rxer to fec n _rxclk setup 5?ns m2 fec n _rxclk to fec n _rxd[3:0], fec n _rxdv, fec n _rxer hold 5?ns m3 fec n _rxclk pulse width high 35% 65% fec n _rxclk period m4 fec n _rxclk pulse width low 35% 65% fec n _rxclk period r1 r2 clkout reset rstout r3 r4 r8 r7 r6 r5 configuration overrides 1 : r4 (rcon, override pins]) 1. refer to the coldfire integration module (cim) section for more information.
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 64 figure 17. mii receive signal timing diagram 10.11.2mii transmit signal timing (fec n _txd[3:0], fec n _txen, fec n _txer, fec n _txclk) table 55 lists mii transmit channel timings. the transmitter functions correctly up to a fec n _txclk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the processor clock fr equency must ex ceed twice the fec n _txclk frequency. the transmit outputs (fec n _txd[3:0], fec n _txen, fec n _txer) can be programmed to transition from either the rising or falling edge of fec n _txclk, and the timing is the same in either case. this options allows the use of non-compliant mii phys. refer to the ethernet chapter for detail s of this option and how to enable it. figure 18 shows mii transmit si gnal timings listed in table 55 . table 55. mii transmit channel timings. num characteristic min max unit m5 fec n _txclk to fec n _txd[3:0], fec n _txen, fec n _txer invalid 5?ns m6 fec n _txclk to fec n _txd[3:0], fec n _txen, fec n _txer valid ?25ns m7 fec n _txclk pulse width high 35% 65% fec n _txclk period m8 fec n _txclk pulse width low 35% 65% fec n _txclk period m1 m2 fec n _rxclk (input) fec n _rxd[3:0] (inputs) fec n _rxdv fec n _rxer m3 m4
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 65 figure 18. mii transmit signal timing diagram 10.11.3mii async inputs signal timing (fec n _crs and fec n _col) table 56 lists mii asynchronous inputs signal timing. figure 19 shows mii asynchronous i nput timings listed in table 56 . figure 19. mii async inputs timing diagram 10.11.4mii serial management channel timing (fec n _mdio and fec n _mdc) table 57 lists mii serial management channel timings. the fec functio ns correctly with a maximum mdc frequency of 2.5 mhz. table 56. mii asynchronous input signal timing num characteristic min max unit m9 fec n _crs, fec n _col minimum pulse width 1.5 ? fec n _txclk period table 57. mii serial management channel timings. num characteristic min max unit m10 fec n _mdc falling edge to fec n _mdio output invalid (minimum propagation delay) 0?ns m11 fec n _mdc falling edge to fec n _mdio output valid (max prop delay) ? 25 ns m12 fec n _mdio (input) to fec n _mdc rising edge setup 10 ? ns m13 fec n _mdio (input) to fec n _mdc rising edge hold 0 ? ns m6 fec n _txclk (input) fec n _txd[3:0] (outputs) fec n _txen fec n _txer m5 m7 m8 fec n _crs, fec n _col m9
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 66 figure 20 shows mii serial management channel timings listed in table 57 . figure 20. mii serial management channel timing diagram 10.11.5usb interface ac timing specifications table 58 lists usb interface timings. m14 fec n _mdc pulse width high 40% 60% mdc period m15 fec n _mdc pulse width low 40% 60% mdc period table 58. usb interface timings. num characteristic min max units us1 usb_clk frequency of operation 48 48 mhz us2 usb_clk fall time (v ih = 2.4 v to v il = 0.5 v) ? 2 ns us3 usb_clk rise time (v il = 0.5 v to v ih = 2.4 v) ? 2 ns us4 usb_clk duty cycle (at 0.5 x o v dd )4555% data inputs us5 usb_rp, usb_rn, usb_rxd valid to usb_clk high 6 ? ns us6 usb_clk high to usb_rp, usb_rn, usb_rxd invalid 6 ? ns data outputs table 57. mii serial management channel timings. num characteristic min max unit m11 fec n _mdc (output) fec n _mdio (output) m12 m13 fec n _mdio (input) m10 m14 m15
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 67 figure 21 shows usb interface timings listed in table 58 . figure 21. usb signals timing diagram 10.12 i 2 c input/output timing specifications table 59 lists specifications for the i 2 c input timing parameters shown in figure 22 . us7 usb_clk high to usb_tp, usb_tn, usb_susp valid ? 12 ns us8 usb_clk high to usb_tp, usb_tn, usb_susp invalid 3 ? ns table 59. i 2 c input timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 start condition hold time 2 x t cyc ?ns i2 clock low period 8 x t cyc ?ns i3 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms table 58. usb interface timings. num characteristic min max units us7 usb_clk usb outputs us8 us5 us6 usb inputs t rise v h = v ih v l = v il t fall v h = v ih v l = v il input rise time input fall time us1
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 68 table 60 lists specifications for the i 2 c output timing parameters shown in figure 22 . figure 22 shows timing for the values in table 59 and table 60 . i6 clock high time 4 x t cyc ?ns i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 x t cyc ?ns i9 stop condition setup time 2 x t cyc ?ns table 60. i 2 c output timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 1 notes: 1 note: output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta b l e 6 0 . the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the i2c_scl low period. the actual position is affected by the prescale and division values programmed into the ifdr; however, the numbers given in ta b l e 6 0 are minimum values. start condition hold time 6 x t cyc ?ns i2 1 clock low period 10 x t cyc ?ns i3 2 2 because i2c_scl and i2c_sda are open-collector-t ype outputs, which the processor can only actively drive low, the time i2c_scl or i2c_sda take to reach a high level depends on external signal capacitance and pull-up resistor values. i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ??s i4 1 data hold time 7 x t cyc ?ns i5 3 3 specified at a nominal 50-pf load. i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ?3ns i6 1 clock high time 10 x t cyc ?ns i7 1 data setup time 2 x t cyc ?ns i8 1 start condition setup time (for repeated start condition only) 20 x t cyc ?ns i9 1 stop condition setup time 10 x t cyc ?ns table 59. i 2 c input timing specifications between i2c_scl and i2c_sda num characteristic min max units
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 69 figure 22. i 2 c input/output timings 10.13 dma timers timing specifications table 61 lists timer module ac timings. 10.14 qspi electrical specifications table 62 lists qspi timings. the values in table 62 correspond to figure 23 . table 61. timer module ac timing specifications name characteristic 1 notes: 1 all timing references to clkout are given to its rising edge. min max unit t1 t0in / t1in / t2in / t3in cycle time 3 x t cyc ?ns t2 t0in / t1in / t2in / t3in pulse width 1 x t cyc ?ns table 62. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[3:0] to qspi_clk 1 510 t cyc qs2 qspi_clk high to qspi_dout valid. ? 10 ns qs3 qspi_clk high to qspi_dout invalid (output hold) 2 ? ns qs4 qspi_din to qspi_clk (input setup) 9 ? ns qs5 qspi_din to qspi_clk (input hold) 9 ? ns i2 i6 i1 i4 i7 i8 i9 i5 i3 scl sda
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 70 figure 23. qspi timing 10.15 jtag and boundary scan timing table 63. jtag and boundary scan timing num characteristics 1 notes: 1 jtag_en is expected to be a static signal. he nce, it is not associated with any timing. symbol min max unit j1 tclk frequency of operation f jcyc dc 1/4 f sys/2 j2 tclk cycle period t jcyc 4 x t cyc -ns j3 tclk clock pulse width t jcw 26 - ns j4 tclk rise and fall times t jcrf 03ns j5 boundary scan input data setup time to tclk rise t bsdst 4-ns j6 boundary scan input data hold time after tclk rise t bsdht 26 - ns j7 tclk low to boundary scan output data valid t bsdv 033ns j8 tclk low to boundary scan output high z t bsdz 033ns j9 tms, tdi input data setup time to tclk rise t tapbst 4-ns j10 tms, tdi input data hold time after tclk rise t tapbht 10 - ns j11 tclk low to tdo data valid t tdodv 026ns j12 tclk low to tdo high z t tdodz 08ns j13 trst assert time t trstat 100 - ns j14 trst setup time (negation) to tclk high t trstst 10 - ns qspi_cs[3:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 71 figure 24. test clock input timing figure 25. boundary scan (jtag) timing tclk v il v ih j3 j3 j4 j4 j2 (input) input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j5 j6 j7 j8 j7
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary preliminary electrical characteristics freescale semiconductor 72 figure 26. test access port timing figure 27. trst timing 10.16 debug ac timing specifications table 64 lists specifications for the de bug ac timing parameters shown in figure 29 . table 64. debug ac timing specification num characteristic 166 mhz units min max d0 pstclk cycle time 0.5 t cyc d1 pst, ddata to clkout setup 4 ns d2 clkout to pst, ddata hold 1.5 ns d3 dsi-to-dsclk setup 1 x t cyc ns d4 1 dsclk-to-dso hold 4 x t cyc ns input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst 14 13
preliminary electrica l characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary freescale semiconductor 73 figure 28 shows real-time trace timing for the values in table 64 . figure 28. real-time trace ac timing figure 29 shows bdm serial port ac timing for the values in table 64 . figure 29. bdm serial port ac timing d5 dsclk cycle time 5 x t cyc ns d6 bkpt input data setup time to clkout rise 4 ns d7 bkpt input data hold time to clkout rise 1.5 ns d8 clkout high to bkpt high z 0.0 10.0 ns notes: 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of clkout. table 64. debug ac timing specification num characteristic 166 mhz units min max clkout pst[3:0] d2 d1 ddata[3:0] dsi dso current next clkout past current dsclk d3 d4 d5
mcf5275 integrated microprocessor fami ly hardware specification, rev. 1.1 preliminary device/family documentation list freescale semiconductor 74 11 device/family documentation list 12 document revision history table 66 provides a revision history fo r this hardware specification. table 65. mcf5275 documentation motorola document number title revision status mcf5275ec/d mcf5275 risc microprocessor hardware specifications 0 this document mcf5275rm/d mcf5275 reference manual 0 in process mcf5275pb/d mcf5275 product brief 0 available mcf5275fs mcf5275 fact sheet 0 in process cfprodfact/d the coldfire family of 32-bit microprocessors family overview and technology roadmap 0 available mcf5xxxwp mcf5xxxwp white pape r: motorola coldfire vl risc processors 0 available mapbgapp mapbga 4-layer example 0 available cfprm/d coldfire family programmer's reference manual 2 available table 66. document revision history rev. no. substantive change(s) 1.1 removed duplicate information in the module descr iption sections. the information is all in the signals description table. 1 added figure 6 0 initial release.
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mcf5275ec/d rev. 1.1, 9/2004 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor h.k. ltd. 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 learn more: for more information about freescale semiconductor products, please visit http://www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or s pecifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004. preliminary

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